1. Field of the Invention
The present invention relates to a phase differencexe2x80x94current conversion circuit used for a PLL circuit or the like.
2. Description of the Related Art
FIG. 10 is a circuit diagram showing a conventional phase differencexe2x80x94current conversion circuit. Hereinafter, a description will be made with reference to this drawing.
The conventional phase differencexe2x80x94current conversion circuit includes a phase comparator 50 for outputting a digital signal corresponding to a phase difference of two signals, a charge pump circuit 54 for outputting a current as an analog signal corresponding to the digital signal outputted from the phase comparator 50, and a reset circuit 52 as a delay circuit for resetting the digital signal outputted from the phase comparator 50 after a definite delay time in the case where the phases of the two signals have coincided with each other.
The phase comparator 50 is a general digital phase comparator constituted by NAND gates 501 and 508, and inverters 509 and 510. In the case where the phases of input signals from terminals Sig and Ref do not coincide with each other, one of terminals Up and Down becomes an H level and the other becomes an L level. In the case where the phases of the input signals from the terminals Sig and Ref coincide with each other, both the terminals Up and Down become the H level first, and become the L level after the definite delay time.
The charge pump circuit 54 is a current mirror circuit constituted by transistors M5 to M8, current sources 541 and 542, electric switches SW2 and SW3, and the like. In the case where the terminals Up and Up1 are in the H level, and the terminals Down and Down1 are in the L level, the electric switch SW2 is turned off, and the electric switch SW3 is turned on, so that a current Iup flows out from a terminal CPOUT. On the contrary, in the case where the terminals Up and Up1 are in the L level, and the terminals Down and Down1 are in the H level, the electric switch SW2 is turned on and the electric switch SW3 are turned off, so that a current Idown flows in from the terminal CPOUT. In the case where both the terminals Up and Up1 and the terminals Down and Down1 are in the H level, both the electric switches SW2 and SW3 are turned on, so that the current Idown and the current Iup cancel out each other, and a slight difference between those currents is outputted from the terminal CPOUT. On the contrary, in the case where both the terminals Up and Up1 and the terminals Down and Down1 are in the L level, since both the electric switches SW2 and SW3 are turned off, nothing is outputted from the terminal CPOUT.
The reset circuit 52 is constituted by 2n inverters 521 to 52n connected in series. Conventionally, the number of stages of the inverters 521, . . . or the size of transistors constituting the inverters 521, . . . are adjusted, so that the delay time is adjusted.
A delay time of the reset circuit 52 is set so that the time is equal to a rising delay time of the output current of the charge pump circuit 54. At this time, even in the lock state of PLL in which the input signals from the terminals Sig and Ref of the phase comparator 50 come to have the same phase, the charge pump circuit 54 responds to a very slight phase difference of the input signals from the terminals Sig and Ref, and comes to output a current in proportion to the phase difference. By this, it is possible to avoid a state generally called a dead band in which output current is not in proportion to a phase difference.
Next, problems of the conventional technique will be described.
A first problem is as follows: At the time of PLL lock, a current flowing through the transistor of the output stage of the charge pump is required to have such characteristics that it is cut off after reaching a previously set current value. However, by change of operation conditions of fluctuation of conditions at the time of manufacture, it has not been able to keep the characteristics. This has caused deterioration of noise characteristics.
The reason why the first problem occurs will be described. The delay time of the reset circuit is determined by the gate capacitance of a PMOS transistor and an NMOS transistor constituting an inverter, and the on resistance of a PMOS transistor of the upstream stage inverter. On the contrary, the current rising delay time of the charge pump circuit is determined by a reference current value of the current mirror circuit and gate capacitance of a transistor constituting the current mirror circuit. That is, since the principle based on which the current rising delay time is generated is different between the reset circuit and the charge pump circuit, when power supply voltage, ambient temperature, manufacturing conditions, and the like are changed, the delay time of the reset circuit and the current rising delay time of the charge pump circuit are changed independently from each other. Thus, it has not been able to keep such characteristics that the current flowing through the transistor of the charge pump output stage at the time of PLL lock is cut off after reaching a set current value.
A second problem is as follows: The inverter used as a delay element in the reset circuit has a delay amount per stage for smaller than the current rising delay time of the charge pump circuit. Thus, since several tens stages become necessary for the number of stages of the inverters, it is difficult to set a time in which a charge pump output current at the PLL lock flows, to the optimum length.
The reason why the second problem occurs will be described. When the output current of the charge pump circuit is tried to be set large so as to increase the suppression effect of noise generated in the charge pump circuit, it is necessary to increase the channel width W of a transistor at the output stage. By this, since the gate capacitance of the transistor is increased, the current rising delay time of the charge pump circuit becomes large. On the other hand, in order to cause the reset circuit to generate this delay time, the inverters of several tens stages become necessary. However, it is difficult to form such inverters of several tens stages on a semiconductor chip since a space is not sufficient. As a result, it becomes difficult to keep the time in which the charge pump output current flows at the time of PLL lock, to the optimum length.
An object of the present invention is therefore to provide a phase differencexe2x80x94current conversion circuit which can always realize such characteristics that a current flowing through a transistor at a charge pump output stage reaches a set value at the time of PLL lock and is cut off, without increasing an occupied area on a semiconductor chip.
A phase differencexe2x80x94current conversion circuit according to the present invention includes a phase comparator for outputting first and second digital signals one of which has a first level and the other of which has a second level in a case where phases of two input signals do not coincide with each other, and for outputting the first and second digital signals both of which have the first level in a case where the phases of the two input signals coincide with each other; a charge pump circuit for outputting an outflow current only when the first digital signal outputted from the phase comparator is in the first level, and outputting an inflow current only when the second digital signal outputted from the phase comparator is in the first level; and a delay circuit for causing the first and second digital signal outputted from the phase comparator to become the second level after a definite delay time in a case where the phases of the two input signals coincide with each other. The charge pump circuit is provided with a current outputting transistor for gently outputting the outflow current or the inflow current by its rising delay time. The delay circuit is provided with a delay time determining transistor for determining the definite delay time by its rising delay time. The rising delay time of the delay time determining transistor is set equal to the rising delay time of the current outputting transistor.
Since the rising delay time of the current outputting transistor of the charge pump circuit is set equal to the rising delay time of the delay time determining transistor of the delay circuit, even in the case where the delay characteristics of the current outputting transistor are changed by power supply voltage, ambient temperature, manufacturing conditions and the like, the delay characteristics of the delay time determining transistor are also changed in the same way, Because, when compared with the conventional technique, the current outputting transistor and the delay time determining transistor are transistors having the same rising delay time, changing factors of the delay characteristics are common to the charge pump circuit and the delay circuit. By this, such characteristics that an output current of the charge pump circuit reaches a set value and is cut off is always kept.
In order to cause the changes of delay characteristics of the current outputting transistor and the delay time determining transistor to become more coincident with each other, it is preferable to form the delay time determining transistors and the current outputting transistor on the same semiconductor chip, and further, it is most preferable to form them with the same structure on the same semiconductor chip at the same time.
The phase differencexe2x80x94current conversion circuit according to the present invention further adopts the following structure. The current outputting transistor is constituted by a first conductivity type current outputting transistor for outputting the outflow current only when the first digital signal outputted from the phase comparator is in the first level, and a second conductivity type current outputting transistor for outputting the inflow current only when the second digital signal outputted from the phase comparator is in the first level. The delay time determining transistor is constituted by a first conductivity type delay time determining transistor and a second conductivity type delay time determining transistor which are operated by the first and second digital signals outputted from the phase comparator in the case where the phases of the two input signals coincide with each other. The delay circuit is provided with delay time determining means for setting a longer one of a delay time determined by the first conductivity type delay time determining transistor and a delay time determined by the second conductivity type delay time determining transistor to the delay time of the delay circuit.
When a difference occurs in, for example, threshold values between the first and second conductivity type current outputting transistors due to difference in the conductivity type, a difference occurs in the rising delay time as well. At this time, similarly, a difference occurs in the rising delay time in the first and second conductivity type delay time determining transistors as well. On the other hand, the delay time determining means sets a longer one of the delay times determined by the first and second conductivity type delay time determining transistors to the delay time of the delay circuit. Thus, even if one of the first and second conductivity type current outputting transistors is operated, since the delay circuit is always operated in accordance with the slower one, such characteristics that the output current of the charge pump circuit reaches a set value and is cut off are always kept.
The phase differencexe2x80x94current conversion circuit according to the present invention further adopts the following structure. The output signal of the delay circuit to bring the first and second digital signals outputted from the phase comparator in the case where the phases of the two input signals coincide with each other into the second level after the definite delay time is changed from the second level to the first level after the definite delay time when both the first and second digital signals are changed from the second level to the first level, and subsequently, it returns to the second level instantaneously when both the first and second digital signals are changed from the first level to the second level.
When the output signal of the delay circuit is made delayed at, for example, only the rising edge of the input signal and is not delayed at the falling edge, as compared with the case where it is delayed also at the falling edge, the operation of the phase differencexe2x80x94current conversion circuit becomes possible at an about double frequency.
The phase differencexe2x80x94current conversion circuit according to the present invention further adopts the following structure. The delay time determining transistor is provided with a gate capacitance increasing transistor, a gate of the delay time determining transistor is connected to a gate of the capacitance increasing transistor, and a source of the delay time determining transistor is connected to a source and drain of the capacitance increasing transistor.
Since the source and drain of the capacitance increasing transistor are connected to the source of the delay time determining transistor, a drain current does not flow. In addition, since the gate of the capacitance increasing transistor is connected to the gate of the delay time determining transistor, a gate current transiently flows. On the other hand, a rising delay time of a transistor is in proportion to a gate capacitance (product of channel length and channel width), and is in inverse proportion to a steady drain current. Thus, in the delay time determining transistor, the gate capacitance can be substantially adjusted without increasing the drain current. By this, while low consumed electric power is realized, a desired rising delay time can be obtained.
The phase differencexe2x80x94current conversion circuit according to the present invention further adopts the following structure. The delay time determining transistor is designed such that, with respect to the current outputting transistor, providing that k greater than 1, a steady drain current is made 1/k, and a product of a channel length and a channel width is made 1/k.
A rising delay time of a transistor is in proportion to gate capacitance (product of channel length and channel width), and is in inverse proportion to a steady drain current. That is, even if the steady drain current is made 1/k, and the product of the channel length and the channel width is made 1/k, the rising delay time of the transistor is not changed. Further, low consumed electric power and miniaturization can be realized.
In the above structure, the first level may be a high potential, and the second level may be a low potential, and on the contrary, the first level may be a low potential, and the second level may be a high potential. In addition, the first conductivity type may be a p-channel type and the second conductivity type may be an n-channel type, and on the contrary, the first conductivity type may be an n-channel type, and the second conductivity type may be a p-channel type.
Next, the invention will be described once more using different expression.
(1) The phase differencexe2x80x94current conversion circuit is characterized by having such a circuit structure that even in the case where power supply voltage, ambient temperature, manufacturing conditions, and the like are changed, delay characteristics of the delay circuit used as a reset circuit of the phase comparator is changed at the same ratio as rising delay characteristics of output current of the charge pump circuit. In the present invention, even in the case where power supply voltage, ambient temperature, manufacturing conditions, and the like are changed, it is possible to always keep such characteristics that the current flowing through the transistor of the charge pump output stage at the time of PLL lock reaches a set value and is cut off.
(2) The delay circuit of the phase comparator used in the phase differencexe2x80x94current conversion circuit of the above paragraph (1) is characterized by the following circuit structure. Here, the size of a transistor is defined as a product LW of a channel length L and a channel width W. In addition, a mirror ratio is defined as a ratio (channel length L is constant) of channel widths W of input and output transistors used in a current mirror circuit.
A. As shown in a delay circuit of FIG. 1, there is provided a circuit structure in which a delay of a mirror current of a current mirror circuit constituted by transistors is detected, thereby to obtain a delay time.
B. As shown in FIG. 1, a transistor M3 for setting the delay time is connected to transistors M1 and M2 constituting the current mirror circuit of the delay circuit, and a drain of the transistor M3 is connected to GND. By this, delay characteristics comparable to a current mirror circuit having a large mirror ratio are realized without increasing a consumed current. In the current mirror circuit of the delay circuit of FIG. 1, although the ratio of current I1 and I2 becomes 1:n2 (2 of n2 means 2 of the transistor M2, that is, 1:n2 means that the channel width of the transistor M2 is n times as large as that of the transistor M1), the delay time of the mirror current I2 becomes almost equal to that of a current mirror circuit having a mirror ratio of 1:(n2+n3).
C: For the purpose of reducing a mounting area on a semiconductor integrated circuit without increasing a consumed current of the delay circuit while the delay time of the delay circuit and that of the charge pump circuit are kept the same, the circuit of FIG. 1 is made the structure described below. Since the mirror ratio of the current mirror circuit of charge pump output stage transistors M7 and M8 is 1:n8, the mirror ratio of M1, M2, and M3 of the delay circuit is adjusted, and is set so that M1 and (M2+M3) have a mirror ratio of 1:n8. In the case where the size ratio of M1 and M7 is set to 1; k, reference current IO of the delay circuit is set to 1/k of reference current Icp of the charge pump.
D. The characteristics of the delay circuit of FIG. 1 are made such that only the rising edge of an input signal is delayed, and the falling edge of the delayed signal falls down at the same time as the input signal. In the delay circuit of FIG. 1, AND of the input signal and the signal of the delayed input is taken, so that the characteristics of delaying only the rising edge of the input signal are realized. When the input is changed to the L level by INV2 and M4, electric charges stored in the gate of M1, M2 and M3 are discharged by M4, and the circuit is instantaneously made an off state, so that lowering of a consumed current is realized. Since the delay circuit is made such a structure that the falling edge is not delayed, so compared with the case where the falling edge is also delayed, the phase differencexe2x80x94current conversion circuit can operate at an about double frequency.
E. In FIG. 1, in the case where the reference current Icp of the charge pump is made variable, the reference current IO of the delay circuit is also made to follow this, and is made variable at the same ratio as the reference current of the charge pump. By carrying out this control, even in the case where a set current of the charge pump circuit is made variable, it is possible to keep such characteristics that the current flowing through the transistor of the charge pump output stage at the time of PLL lock reaches a set value and is cut off.
F. As shown in FIG. 4, a delay circuit is characterized in that a delay circuit of an NMOS mirror circuit and a delay circuit of a PMOS mirror circuit are operated at the same time, and a longer delay time is selected and is outputted. By replacing the delay circuit of the phase differencexe2x80x94current conversion circuit of FIG. 1 with the circuit of FIG. 4, even in the case where threshold voltages of NMOS transistors and PMOS transistors are separately changed, it is possible to realize such characteristics that the current flowing through the transistor of the charge pump output stage at the time of PLL lock reaches a set value, and then, it is cut off.
In the case where the delay circuit of FIG. 1 is replaced with the delay circuit of FIG. 4, for the purpose of reducing a mounting area on a semiconductor integrated circuit without increasing a consumed current of the delay circuit while the delay time of the delay circuit and that of the charge pump circuit are kept the same, the structure described below is adopted. Since the mirror ratio of the current mirror current of M7 and M8 using NMOS transistors of the charge pump circuit shown in FIG. 1 is 1:n8, the mirror ratio of M9, M10, and M11 of the NMOS delay circuit in FIG. 4 is adjusted, and is set so that the mirror ratio of M9 and (M10+M11) becomes 1:n8. Since the mirror ratio of the current mirror circuit of M5 and M6 using the PMOS transistors of the charge pump circuit shown in FIG. 1 is 1:n6, the mirror rate of M12, M13, and M14 of the PMOS delay circuit in FIG. 4 is adjusted and is set so that the mirror ratio of M12 and (M13+M14) becomes 1:n6. In the case where the size ratio of M7 and M9 is set to 1:kn, the reference current In of the NMOS delay circuit is set to 1/kn of the reference current Icp of the charge pump. In the case where the size of ratio of M5 and M12 is set to 1:kp, a reference current Ip of the PMOS delay circuit is set to 1/kp of the reference current of the charge pump.